Comparison of CISC vs. RISC Architecture

Both RISK (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) are CPU architectures with different design philosophies. RISK design principles is based on the idea that it more efficient to execute a large number of simplified infrastructures instead of single complex instruction. One famous example which inspired RISK architecture philosophy is DEC VAX index instruction which was, according to John Bayko (2003), 45% to 60% faster when replaced by a number of simple instructions in a loop. As a result of larger number of instructions, execution program were more complex and required more main memory space. Examples of CPU based on the RISK design are DEC Alpha, ARC, ARM, AVR, MIPS, Power, and SPARC.
CISC, on the other hand, is a direct competitor to RISK. It is based on a general lack of main memory to store large number of instructions when executing the program. Instead, a single instruction would result in number of low level operations such as memory read, arithmetic operation and memory write, resulting in a more dense code. In addition, high level programming languages were not available in the early days of the computer history therefore hardware designers tried to architect a set of complex instructions that would do as much as possible on behalf of compilers. CISC as a term was mainly used to contrast to RISK architecture and was basically used to described computer architectures such as the IBM S/370, DEC VAX, Intel x86, and Motorola 680.
The main strengths of the RISK architecture are in the number of available registers and the computation speed (of simple instructions). The disadvantage, as note previously, is a larger code size resulting in higher memory requirements. Although previously RISK based architecture was assosiated with a more complex development process, it slowly becomes irrelevant with introduction of higher level software development languages. Since RISK architecture excels in higher throughput of arithmetic actions (both integer and float point), is more applicable to systems requiring high computing power such as image processing, biological and geographical simulations, and trading applications.
The fundamental advantage of CISC architecture is a more dense code with requires fewer accessed to main memory, and although there are constant advancements in the RAM technology, both in clock speed and size, the main memory is still slower then CPU registers. The disadvantages are a more complex hardware architecture and the need to translate (transcode) even a single simple instruction which make CISC processors less efficient than RISK. Based on that, CISC processors are more applicable to desktop environment where frequent access to main memory is required.
However, according to Gao Y., Tang S. and Ding Z. (n.d.) “In 90's, the trend is migrating toward each other, RISC machines may adopt some traits from CISC, while CISC may also do it vice versa”. This is evident in the evolution of the Intel microprocessors which are converting, starting with Intel Pro family, CISC based instructions to micro-ops (RISC instructions).

Bibliography

• Bayko, J. (2003), Great Microprocessors of the Past and Present (V 13.4.0) [online]. Available at: http://www.cpushack.com/CPU/cpu.html (accessed on 16 October 2010).
  
• DeMone P. (2000), RISC vs. CISC Still Matters [online]. Available at: http://www.realworldtech.com/page.cfm?ArticleID=RWT021300000000 (accessed on 16 October 2010).
  
• Gao Y., Tang S. and Ding Z. (n.d.), Comparison between CISC and RISC [online], Available at: http://www.cc.gatech.edu/grads/z/Howard.Zhou/micellaneous/gre_cs_sub/risc_cisc.pdf (accessed on 16 October 2010).
• Wikipedia (n.d.), Reduced instruction set computing [online], Available at: http://en.wikipedia.org/wiki/Reduced_instruction_set_computing (accessed on 16 October 2010).
• Wikipedia (n.d.), Complex instruction set computing [online]. Available at: http://en.wikipedia.org/wiki/Complex_instruction_set_computer (accessed on 16 October 2010).